1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and particularly relates to a manufacturing method of a semiconductor device including a first protrusion and a second protrusion higher than the first protrusion.
2. Related Background Art
There exists a FinFET in which a gate electrode and source/drain regions are three-dimensionally formed to improve the degree of integration of field effect transistors (For example, see Japanese Patent Application Laid-open No. 2002-9289, Japanese Patent Application No. 2004-150519). A FinFET has two protrusions, the source/drain region of the Fin and the gate electrode. The gate electrode as a second protrusion is formed higher than the Fin as a first protrusion.
When a sidewall is formed on a side surface of the gate electrode in such a FinFET, a sidewall is also formed on a side surface of the Fin, which causes a problem that application of doping and silicidation to the source/drain regions on the Fin is difficult. Namely, doping and silicide formation can be performed only on an upper surface of the Fin.
However, by application of doping and silicidation in the aforementioned manner, it is very difficult to form the uniform source/drain regions in a depth direction of the Fin, and, in usual, the effective channel length between the source and the drain region differ depending on the depth of the Fin. A lower portion of the Fin has a high series resistance, and the resistance degrade the drive current of the FinFET.
Such problems may arise not only in the FinFET but also in semiconductor devices including plural protrusions with different heights.